Cadence announced immediate availability of the 65-nanometer Common Power Format (CPF) enabled reference flow targeting the Common Platform technology. This reference flow is the next step in the ongoing collaboration between Cadence and the Common Platform coalition comprised of IBM, Chartered Semiconductor Manufacturing and Samsung. Cadence worked closely with the Common Platform technology partners to develop this 65-nanometer flow. It is based on the Cadence digital IC design platform including Encounter Timing System and CPF to accelerate time to market for low-power system-on-chip (SoC) designs.